Many decode circuits include multiple transistors arrayed such that a combination of activated transistors produce a logical function. Such transistors in the array are activated, in the case of MOSFET devices, by either applying or not applying a potential to the gate of the MOSFET. This action either turns on the transistor or turns off the transistor. Conventionally, each logical input to the decode circuit is applied to an independent MOSFET gate. Thus, according to the prior art, a full MOSFET is required for each input to the decode circuit. Requiring a full MOSFET for each logic input consumes a significant amount of chip surface area. Conventionally, the size of each full MOSFET, e.g. the space it occupies, is determined by the minimum lithographic feature dimension. Thus, the number of logical functions that can be performed by a given decode circuit is dependent upon the number of logical inputs which is dependent upon the available space to in which to fabricate an independent MOSFET for each logic input. In other words, the minimum lithographic feature size and available surface determine the functionality limits of the decode circuit.
Pass transistor logic is one of the oldest logic techniques and has been described and used in NMOS technology long before the advent of the CMOS technology currently employed in integrated circuits. A representative article by L. A. Glasser and D. W. Dobberpuhl, entitled "The design and analysis of VLSI circuits," Addison-Wesley, Reading Mass., 1985, pp. 16-20, describes the same. Pass transistor logic was later described for use in complementary pass transistor circuits in CMOS technology. Articles which outline such use include articles by J. M. Rabaey, entitled "Digital Integrated Circuits; A design perspective," Prentice Hall, Upper Saddle River, N.J., pp. 210-222, 1996, and an article by K. Bernstein et al., entitled "High-speed design styles leverage IBM technology prowess," MicroNews, vol. 4, no. 3, 1998. What more, there have been a number of recent applications of complementary pass transistor logic in microprocessors. Articles which describe such applications include articles by T. Fuse et al., entitled "A 0.5V 200 mhz 1-stage 32b ALU using body bias controlled SOI pass-gate logic," Dig. IEEE Int. Solid-State Circuits Conf., San Francisco, pp. 286-287, 1997, an article by K. Yano et al., entitled "Top-down pass-transistor logic design," IEEE J. Solid-State Circuits, Vol. 31, no. 6, pp. 792-803, June 1996, and an article by K. H. Cheng et al., entitled "A 1.2V CMOS multiplier using low-power current-sensing complementary pass-transistor logic", Proc. Third Int. Conf. On Electronics, Circuits and Systems, Rodos, Greece, 13-16 Oct., vol. 2, pp. 1037-40, 1996.
In another approach, differential pass transistor logic has been developed to overcome concerns about low noise margins in pass transistor logic. This has been described in an article by S. I. Kayed et al., entitled "CMOS differential pass-transistor logic (CMOS DPTL) predischarge buffer design," 13th National Radio Science Conf., Cairo, Egypt, pp. 527-34, 1996, as well as in an article by V. G. Oklobdzija, entitled "Differential and pass-transistor CMOS logic for high performance systems," Microelectronic J., vol. 29, no. 10, pp. 679-688, 1998. Combinations of pass-transistor and CMOS logic have also been described. S. Yamashita et al., "Pass-transistor? CMOS collaborated logic: the best of both worlds," Dig. Symp. On VLSI Circuits, Kyoto, Japan, 12-14 June, pp. 31-32, 1997. Also, a number of comparisons of pass transistor logic and standard CMOS logic have been made for a variety of different applications and power supply voltages. These studies are described in an article by R. Zimmerman et al., entitled "Low-power logic styles: CMOS versus pass transistor logic," IEEE J. Solid-State Circuits, vol. 32, no. 7, pp. 1079-1790, July 1997, and in an article by C. Tretz et al., "Performance comparison of differential static CMOS circuit topologies in SOI technology," Proc. IEEE Int. SOI Conference, Oct. 5-8, FL, pp. 123-4, 1998.
However, all of these studies and articles on pass transistor logic have not provided a solution to the constraints placed on decode circuits by the limits of the minimum lithographic feature size and the deficit in the available chip surface space.
An approach which touches upon overcoming the limits of the minimum lithographic feature size and the deficit in the available chip surface space, is disclosed in the following co-pending, commonly assigned U.S. patent applications by Len Forbes and Kie Y. Ahn, entitled: "Programmable Logic Arrays with Transistors with Vertical Gates," attorney docket no. 303.683US1, serial number 09/583,584, "Horizontal Memory Devices with Vertical Gates," Ser. No. 09/584,566, and "Programmable Memory Decode Circuits with Vertical Gates," Ser. No. 09/584,564. Those disclosures are all directed toward a non volatile memory cell structure having vertical floating gates and vertical control gates above a horizontal enhancement mode channel region. In those disclosures one or more of the vertical floating gates is charged by the application of potentials to an adjacent vertical gate. The devices of those disclosures can be used as flash memory, EAPROM, EEPROM devices, programmable memory address and decode circuits, and/or programmable logic arrays. Those applications, however, are not framed to address overcoming the limits of the minimum lithographic feature size and the deficit in the available chip surface space for purposes of pass transistor logic in decode circuits.
Therefore, there is a need in the art to provide improved transistor decode circuit logic which overcomes these barriers.